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MC33272A, MC33274A, NCV33274A Single Supply, High Slew Rate, Low Input Offset Voltage Operational Amplifiers
The MC33272/74 series of monolithic operational amplifiers are quality fabricated with innovative Bipolar design concepts. This dual and quad operational amplifier series incorporates Bipolar inputs along with a patented Zip-R-Trim element for input offset voltage reduction. The MC33272/74 series of operational amplifiers exhibits low input offset voltage and high gain bandwidth product. Dual-doublet frequency compensation is used to increase the slew rate while maintaining low input noise characteristics. Its all NPN output stage exhibits no deadband crossover distortion, large output voltage swing, and an excellent phase and gain margin. It also provides a low open loop high frequency output impedance with symmetrical source and sink AC frequency performance. The MC33272/74 series is specified over -40 to +85C and are available in plastic DIP and SOIC surface mount packages.
Features http://onsemi.com MARKING DIAGRAMS
DUAL PDIP-8 P SUFFIX CASE 626 1 SOIC-8 D SUFFIX CASE 751 1 1 8 8 1 33272 ALYWA 8 MC33272AP AWL YYWW
8
* * * * * * * * * * * * * * * * *
QUAD PDIP-14 P SUFFIX CASE 646 14 1
14 MC33274AP AWLYYWW 1
Pb-Free Packages are Available Input Offset Voltage Trimmed to 100 mV (Typ) Low Input Bias Current: 300 nA Low Input Offset Current: 3.0 nA High Input Resistance: 16 MW Low Noise: 18 nV/ Hz @ 1.0 kHz High Gain Bandwidth Product: 24 MHz @ 100 kHz High Slew Rate: 10 V/ms Power Bandwidth: 160 kHz Excellent Frequency Stability Unity Gain Stable: w/Capacitance Loads to 500 pF Large Output Voltage Swing: +14.1 V/ -14.6 V Low Total Harmonic Distortion: 0.003% Power Supply Drain Current: 2.15 mA per Amplifier Single or Split Supply Operation: +3.0 V to +36 V or 1.5 V to 18 V ESD Diodes Provide Added Protection to the Inputs NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes
14 1 14 MC33274AD AWLYWW 1
SOIC-14 D SUFFIX CASE 751A 14 NCV33274A AWLYWW 1
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2004
1
December, 2004 - Rev. 7
Publication Order Number: MC33272A/D
MC33272A, MC33274A, NCV33274A
PIN CONNECTIONS
DUAL CASE 626/751 Output 1 Inputs 1 VEE
1 2 3 4 - + - + 8 7 6 5
QUAD CASE 646/751A Output 1 Inputs 1
3 1 2 - + - + 14 13
VCC Output 2 Inputs 2
Output 4 Inputs 4
1
4
12 11
(Top View)
VCC Inputs 2
4 5 6 + - + -
VEE Inputs 3 Output 3
10 9 8
2
3
Output 2
7
(Top View)
MAXIMUM RATINGS
Rating Supply Voltage Input Differential Voltage Range Input Voltage Range Output Short Circuit Duration (Note 2) Maximum Junction Temperature Storage Temperature ESD Protection at Any Pin - Human Body Model - Machine Model Maximum Power Dissipation Operating Temperature Range MC33272A, MC33274A NCV33274A PD TA Symbol VCC to VEE VIDR VIR tSC TJ Tstg Vesd 2000 200 Note 2 -40 to +85 -40 to +125 mW C Value +36 Note 1 Note 1 Indefinite +150 -60 to +150 Unit V V V sec C C V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Either or both input voltages should not exceed VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
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MC33272A, MC33274A, NCV33274A
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.)
Characteristics Input Offset Voltage (RS = 10 W, VCM = 0 V, VO = 0 V) (VCC = +15 V, VEE = -15 V) TA = +25C TA = -40 to +85C TA = -40 to +125C (NCV33274A) (VCC = 5.0 V, VEE = 0) TA = +25C Average Temperature Coefficient of Input Offset Voltage RS = 10 W, VCM = 0 V, VO = 0 V, TA = -40 to +125C Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25C TA = Tlow to Thigh Input Offset Current (VCM = 0 V, VO = 0 V) TA = +25C TA = Tlow to Thigh Common Mode Input Voltage Range (DVIO = 5.0 mV, VO = 0 V) TA = +25C Large Signal Voltage Gain (VO = 0 V to 10 V, RL = 2.0 kW) TA = +25C TA = Tlow to Thigh Output Voltage Swing (VID = 1.0 V) (VCC = +15 V, VEE = -15 V) RL = 2.0 kW RL = 2.0 kW RL = 10 kW RL = 10 kW (VCC = 5.0 V, VEE = 0 V) RL = 2.0 kW RL = 2.0 kW Common Mode Rejection (Vin = +13.2 V to -15 V) Power Supply Rejection VCC/VEE = +15 V/ -15 V, +5.0 V/ -15 V, +15 V/ -5.0 V Output Short Circuit Current (VID = 1.0 V, Output to Ground) Source Sink Power Supply Current Per Amplifier (VO = 0 V) (VCC = +15 V, VEE = -15 V) TA = +25C TA = Tlow to Thigh (VCC = 5.0 V, VEE = 0 V) TA = +25C 3. MC33272A, MC33274A NCV33274A Tlow = -40C Tlow = -40C Thigh = +85C Thigh = +125C 6 7 Figure 3 Symbol |VIO| - - - - 3 4, 5 DVIO/DT - IIB - - |IIO| - - VICR VEE to (VCC -1.8) AVOL 90 86 8, 9, 12 VO + VO - VO + VO - 10, 11 VOL VOH CMR PSR 80 16 ISC +25 -25 17 ICC - - - 2.15 - - 2.75 3.0 2.75 +37 -37 - - mA 105 - mA 13.4 - 13.4 - - 3.7 80 13.9 -13.9 14 -14.7 - - 100 - -13.5 - -14.1 0.2 5.0 - dB dB 100 - - - V dB 3.0 - 65 80 V 300 - 650 800 nA 2.0 - nA 0.1 - - - 1.0 1.8 3.5 2.0 mV/C Min Typ Max Unit mV
13 14, 15
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MC33272A, MC33274A, NCV33274A
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.)
Characteristics Slew Rate (Vin = -10 V to +10 V, RL = 2.0 kW, CL = 100 pF, AV = +1.0 V) Gain Bandwidth Product (f = 100 kHz) AC Voltage Gain (RL = 2.0 kW, VO = 0 V, f = 20 kHz) Unity Gain Bandwidth (Open Loop) Gain Margin (RL = 2.0 kW, CL = 0 pF) Phase Margin (RL = 2.0 kW, CL = 0 pF) Channel Separation (f = 20 Hz to 20 kHz) Power Bandwidth (VO = 20 Vpp, RL = 2.0 kW, THD 1.0%) Total Harmonic Distortion (RL = 2.0 kW, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0) Open Loop Output Impedance (VO = 0 V, f = 6.0 MHz) Differential Input Resistance (VCM = 0 V) Differential Input Capacitance (VCM = 0 V) Equivalent Input Noise Voltage (RS = 100 W, f = 1.0 kHz) Equivalent Input Noise Current (f = 1.0 kHz) 30 31 28 29 23, 24, 26 23, 25, 26 27 Figure 18, 33 19 20, 21, 22 Symbol SR 8.0 GBW AVO BW Am fm CS BWP THD - |ZO| Rin Cin en in - - - - - 0.003 35 16 3.0 18 0.5 - - - - - - W MW pF nV/ Hz pA/ Hz 17 - - - - - - 10 24 65 5.5 12 55 -120 160 - - - - - - - - MHz dB MHz dB Deg dB kHz % Min Typ Max Unit V/ms
VCC
Vin
-
+ Vin
+
Sections B C D VO
+
VEE
Figure 1. Equivalent Circuit Schematic (Each Amplifier)
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MC33272A, MC33274A, NCV33274A
P D (MAX), MAXIMUM POWER DISSIPATION (mW) 2400 V IO , INPUT OFFSET VOLTAGE (mV) 2000 MC33272P & MC33274P 1600 1200 800 400 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 MC33274D 5.0 3.0 1.0 2 -1.0 -3.0 -5.0 -55 3 1. VIO > 0 @ 25C 2. VIO = 0 @ 25C 3. VIO < 0 @ 25C VCC = +15 V VEE = -15 V VCM = 0 V 1 1 3 2
MC33272D
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 2. Maximum Power Dissipation versus Temperature
Figure 3. Input Offset Voltage versus Temperature for Typical Units
400 I IB, INPUT BIAS CURRENT (nA) I IB, INPUT BIAS CURRENT (nA) 350 300 250 200 150 100 50 0 -16 VCC = +15 V VEE = -15 V TA = 25C
600 500 400 300 200 100 0 -55 VCC = +15 V VEE = -15 V VCM = 0 V
-12
-8.0
-4.0
0
4.0
8.0
12
16
-25
0
25
50
75
100
125
VCM, COMMON MODE VOLTAGE (V)
TA, AMBIENT TEMPERATURE (C)
Figure 4. Input Bias Current versus Common Mode Voltage
V ICR, INPUT COMMON MODE VOLTAGE RANGE (V)
Figure 5. Input Bias Current versus Temperature
VCC VCC
A VOL, OPEN LOOP VOLTAGE GAIN (X 1.0 kV/V)
180
VCC -0.5 VCC -1.0
160
VCC -1.5
VCC -2.0
140 VCC = +15 V VEE = -15 V RL = 2.0 kW f = 10 Hz DVO = -10 V to +10 V -25 0 25 50 75 100 125
VEE +1.0 VEE +0.5 VEE -55 VEE -25 0 25 50
VCC = +5.0 V to +18 V VEE = -5.0 V to -18 V DVIO = 5.0 mV VO = 0 V 75 100 125
120
100 -55
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 6. Input Common Mode Voltage Range versus Temperature
Figure 7. Open Loop Voltage Gain versus Temperature
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MC33272A, MC33274A, NCV33274A
V sat , OUTPUT SATURATION VOLTAGE (V) 40 VO, OUTPUT VOLTAGE (Vpp ) TA = 25C 30 RL = 10 kW 20 RL = 2.0 kW VCC VCC -1.0 TA = 125C VCC -2.0 VEE +2.0 VEE +1.0 VEE Sink TA = 125C VCC = +5.0 V to +18 V VEE = -5.0 V to -18 V 0 5.0 10 IL, LOAD CURRENT (mA) 15 20 TA = 25C Source TA = -55C
TA = 25C TA = -55C
10
0
0
5.0
10
15
20
VCC, VEE SUPPLY VOLTAGE (V)
Figure 8. Split Supply Output Voltage Swing versus Supply Voltage
Figure 9. Split Supply Output Saturation Voltage versus Load Current
V sat , OUTPUT SATURATION VOLTAGE (V)
TA = 125C TA = 55C
VCC -4.0 VCC -8.0 VCC -12 +0.2 +0.1 Gnd 0 100
VCC VCC = +5.0 V to +18 V RL to Gnd VEE = Gnd
V sat , OUTPUT SATURATION VOLTAGE (V)
VCC
15 14.6 14.2 TA = 25C TA = 55C TA = 125C
8.0 4.0 0 10
TA = 125C TA = +25C TA = -55C 1.0 k 10 k 100 k 1.0 M
TA = 25C TA = -55C
TA = 125C
VCC = +15 V RL to VCC VEE = Gnd RFdbk = 100 kW 10 k 100 k
100
1.0 k
RL , LOAD RESISTANCE TO GROUND (kW)
RL, LOAD RESISTANCE TO VCC (W)
Figure 10. Single Supply Output Saturation Voltage versus Load Resistance to Ground
Figure 11. Single Supply Output Saturation Voltage versus Load Resistance to VCC
CMR, COMMON MODE REJECTION (dB)
28 24 VO, OUTPUT VOLTAGE (Vpp ) 20 16 12 8 4 0 1.0 k VCC = +15 V VEE = -15 V RL = 2.0 kW AV = +1.0 THD = 1.0% TA = 25C 10 k 100 k f, FREQUENCY (Hz) 1.0 M 1 0M
120 100 80 60 40 20 0 10 100 1.0 k 10 k 100 k 1.0 M f, FREQUENCY (Hz)
DVCM + CMR = 20Log DVCM DVO X ADM
TA = 125C
TA = -55C
VCC = +15 V VEE = -15 V VCM = 0 V DVCM = 1.5 V
- ADM DVO
Figure 12. Output Voltage versus Frequency
Figure 13. Common Mode Rejection versus Frequency
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MC33272A, MC33274A, NCV33274A
+PSR, POWER SUPPLY REJECTION (dB) -PSR, POWER SUPPLY REJECTION (dB) 120 TA = 125C 100 80 60 40 20 0
- ADM + VEE +PSR = 20Log DVO/ADM DVCC VCC DVO
120 100 80 60 40 20 0
- ADM + VEE -PSR = 20Log DVO/ADM DVEE VCC DVO
VCC = +15 V VEE = -15 V DVCC = 1.5 V TA = -55C
DVCC = 1.5 V VCC = +15 V VEE = -15 V TA = -55C
TA = 125C
10
100
1.0 k
10 k
100 k
1 .0 M
10
100
1.0 k
10 k
100 k
1.0 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 14. Positive Power Supply Rejection versus Frequency
Figure 15. Negative Power Supply Rejection versus Frequency
|I SC |, OUTPUT SHORT CIRCUIT CURRENT (mA)
60 50 Sink 40 Source 30 20 10 0 -55 Source Sink I CC , SUPPLY CURRENT (mA) VCC = +15 V VEE = -15 V VID = 1.0 V RL < 100 W
11 10 9.0 8.0 7.0 6.0 5.0 4.0 -25 0 25 50 75 100 125 3.0 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 TA = -55C TA = +125C TA = +25C
TA, AMBIENT TEMPERATURE (C)
VCC, |VEE| , SUPPLY VOLTAGE (V)
Figure 16. Output Short Circuit Current versus Temperature
Figure 17. Supply Current versus Supply Voltage
GBW, GAIN BANDWIDTH PRODUCT (MHz)
1.15 SR, SLEW RATE (NORMALIZED) 1.1 1.05 1.0 0.95 0.9 0.85 -55 VCC = +15 V VEE = -15 V DVin = 20 V
DVin - + VO 2.0 kW 100 pF
50 VCC = +15 V VEE = -15 V f = 100 kHz RL = 2.0 kW CL = 0 pF
40 30 20 10 0 -55
-25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
-25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
125
Figure 18. Normalized Slew Rate versus Temperature
Figure 19. Gain Bandwidth Product versus Temperature
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MC33272A, MC33274A, NCV33274A
25 20 15 A V , VOLTAGE GAIN (dB) 10 5.0 0 -5.0 -10 -15 -20 -25 100 k 1.0 M 10 M VCC = +15 V VEE = -15 V RL = 2.0 kW TA = 25C Phase Gain 80 120 140 160 180 200 220 240 260 280 100 M , EXCESS PHASE (DEGREES) 100 25 20 15 A V , VOLTAGE GAIN (dB) 10 5.0 0 -10 1A - Phase V = 18 V, V = -18 V CC EE -15 2A - Phase VCC = 1.5 V, VEE = -1.5 V 1B - Gain VCC = 18 V, VEE = -18 V -20 2B - Gain V = 1.5 V, V = -1.5 V CC EE -25 100 k 1.0 M TA = 25C CL = 0 pF 1A 80 100 140 160 2A 1B 2B 180 200 220 240 , PHASE (DEGREES) 125 120
-5.0
10 M
100 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 20. Voltage Gain and Phase versus Frequency
Figure 21. Gain and Phase versus Frequency
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
20 10 0 2A 1B 2B
100 A m , OPEN LOOP GAIN MARGIN (dB) 120 1A 140 160 180 200 220 240 260 280 20 30 EXCESS PHASE (DEGREES)
12 Gain Margin 10 8.0 6.0 4.0 2.0 Phase Margin 0 1.0 10 100 VCC = +15 V VEE = -15 V VO = 0 V
-
0 10 20 30
VO 2.0 kW CL
VCC = +15 V VEE = -15 V -10 Vout = 0 V TA = 25C 1A - Phase (RL = 2.0 kW) -20 2A - Phase (RL = 2.0 kW, CL = 300 pF) 1B - Gain (RL = 2.0 kW) 2B - Gain (RL = 2.0 kW, CL = 300 pF) -30 3.0 4.0 6.0 8.0 10 f, FREQUENCY (MHz)
Vin
+
40 50
1000
CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 22. Open Loop Voltage Gain and Phase versus Frequency
Figure 23. Open Loop Gain Margin and Phase Margin versus Output Load Capacitance
A m , OPEN LOOP GAIN MARGIN (dB)
12 10 8.0 6.0 4.0 2.0 0 -55 CL = 100 pF CL = 300 pF CL = 500 pF VCC = +15 V VEE = -15 V -25 0 25 50 75 100 125 m, PHASE MARGIN (DEGREES) CL = 10 pF
60 50 40 30 20 10 0 -55 -25 0 25 50 75
CL = 10 pF CL = 100 pF CL = 300 pF CL = 500 pF
VCC = +15 V VEE = -15 V 100
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 24. Open Loop Gain Margin versus Temperature
Figure 25. Phase Margin versus Temperature
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m, PHASE MARGIN (DEGREES)
MC33272A, MC33274A, NCV33274A
15 12 A m , GAIN MARGIN (dB) Phase Margin 9.0 6.0 3.0 0 VCC = +15 V VEE = -15 V RT = R1+R2 VO = 0 V TA = 25C
Vin R1 R2 - + VO
m , PHASE MARGIN (DEGREES)
CS, CHANNEL SEPERATION (dB)
Gain Margin
60 50 40 30 20 10 0 10 k
160 150 140 130 120 110 100 100 Driver Channel VCC = +15 V VEE = -15 V RL = 2.0 kW DVOD = 20 Vpp TA = 25C
1.0
10
100
1.0 k
1.0 k
10 k f, FREQUENCY (Hz)
100 k
1.0 M
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
Figure 26. Phase Margin and Gain Margin versus Differential Source Resistance
Figure 27. Channel Separation versus Frequency
THD, TOTAL HARMONIC DISTORTION (%)
1.0
50 |Z O |, OUTPUT IMPEDANCE ( ) AV = +1000 AV = +100 40 30 20 10 0 10 k AV = 1000 AV = 100 AV = 10 AV = 1.0 VCC = +15 V VEE = -15 V VO = 0 V TA = 25C
0.1 AV = +10 0.01
AV = +1.0 VO = 2.0 Vpp TA = 25C 100 1.0 k f, FREQUENCY (Hz) VCC = +15 V VEE = -15 V 10 k 100 k
0.001 10
100 k
1.0 M
10 M
f, FREQUENCY (Hz)
Figure 28. Total Harmonic Distortion versus Frequency
Figure 29. Output Impedance versus Frequency
e n , INPUT REFERRED NOISE VOLTAGE ( nV/ Hz )
50 + 40 30 20 10 0 VCC = +15 V VEE = -15 V TA = 25C 10 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k -
VO
i n , INPUT REFERRED NOISE CURRENT ( pA/ Hz )
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 VCC = +15 V VEE = -15 V TA = 25C 100
Input Noise Current Circuit RS + - VO
Input Noise Voltage Test Circuit
(RS = 10 kW)
1.0 k f, FREQUENCY (Hz)
10 k
100 k
Figure 30. Input Referred Noise Voltage versus Frequency
Figure 31. Input Referred Noise Current versus Frequency
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MC33272A, MC33274A, NCV33274A
60 PERCENT OVERSHOOT (%) 50 40 30 20 10 0 10 100 CL, LOAD CAPACITANCE (pF) 1000 VCC = +15 V VEE = -15 V RL = 2.0 kW TA = 25C
Figure 32. Percent Overshoot versus Load Capacitance
V O, OUTPUT VOLTAGE (5.0 V/DIV)
VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 kW CL = 100 pF TA = 25C
V O, OUTPUT VOLTAGE (5.0 V/DIV)
CL = 100 pF
VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 kW TA = 25C t, TIME (2.0 ns/DIV)
CL = f
t, TIME (2.0 ms/DIV)
Figure 33. Non-inverting Amplifier Slew Rate for the MC33274
Figure 34. Non-inverting Amplifier Overshoot for the MC33274
V O, OUTPUT VOLTAGE (50 mV/DIV)
t, TIME (2.0 ms/DIV)
V O, OUTPUT VOLTAGE (5.0 V/DIV)
VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 kW CL = 300 pF TA = 25C
VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 kW CL = 300 pF TA = 25C
t, TIME (1.0 ms/DIV)
Figure 35. Small Signal Transient Response for MC33274
Figure 36. Large Signal Transient Response for MC33274
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MC33272A, MC33274A, NCV33274A
ORDERING INFORMATION
Device MC33272AD MC33272ADG MC33272ADR2 MC33272ADR2G MC33272AP MC33272APG MC33274AD MC33274AD MC33274ADR2 MC33274ADR2G MC33274AP NCV33274ADG* NCV33274ADR2* Package SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) PDIP-8 PDIP-8 (Pb-Free) SOIC-14 SOIC-14 SOIC-14 SOIC-14 (Pb-Free) PDIP-14 SOIC-14 (Pb-Free) SOIC-14 Shipping 98 Units / Rail 98 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 55 Units / Rail 55 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 25 Units / Rail 2500 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV devices are automotive qualified.
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MC33272A, MC33274A, NCV33274A
PACKAGE DIMENSIONS
SOIC-8 D SUFFIX CASE 751-07 ISSUE AD
-X- A
8 5
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060 7.0 0.275 4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC33272A, MC33274A, NCV33274A
PACKAGE DIMENSIONS
PDIP-14 P SUFFIX CASE 646-06 ISSUE M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01
14
8
B
1 7
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
SOIC-14 D SUFFIX CASE 751A-03 ISSUE G
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
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MC33272A, MC33274A, NCV33274A
PACKAGE DIMENSIONS
PDIP-8 P SUFFIX CASE 626-05 ISSUE L
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
8
5
-B-
1 4
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M TA B
H
G 0.13 (0.005)
M M
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC33272A/D

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